1. Field of the Invention
The present invention relates to a method for fabricating a gate electrode of a semiconductor device and, more particularly, to a method for fabricating a gate electrode in which source and drain regions can be used independently in need by overlapping a first gate electrode with a second gate electrode.
2. Background of the Related Art
FIG. 1a and FIG. 1b are cross-sectional views illustrating a process of fabricating a gate electrode in accordance with conventional methods.
Referring to FIG. 1a, a gate insulating layer 11, a first conducting layer 12, a first insulating layer 13 and a second insulating layer 14 are sequentially formed on a substrate 10. A gate insulating layer 11 is formed on a substrate 10 with predetermined devices, a first conducting layer 12 for a floating gate electrode is deposited and then a first insulating layer 13 and a second insulating layer 14 are formed to insulate a control gate electrode and the floating gate electrode. Though the gate insulating layer 11 can be made of oxide only or nitride only, the ONO_(Oxide-Nitride-Oxide) structure of upper oxide/nitride/lower oxide is preferably used for the gate insulating layer. Also, the first conducting layer 12 is deposited with silicon, crystallized into polysilicon or single-crystal silicon and etched in a later process to form a floating gate electrode. The first insulating layer 13 is preferably made of oxide and the second insulating layer is preferably made of nitride.
Referring to FIG. 1b, the second insulating layer 14, the first insulating layer 13 and the first conducting layer 12 are sequentially etched to form a gate electrode. The upper part of the second insulating layer 14 is coated with photoresist and a photoresist pattern is formed through exposure and development processes. By using the photoresist pattern as a mask, a floating gate electrode 15 is formed by etching sequentially the second insulating layer 14, the first insulating layer 13 and the first conducting layer 12. The gate insulating layer 11 made of oxide can be used for an etch stop layer during the etching process.
However, the above-described conventional gate forming method has a problem that locations of a source, a drain and a channel are fixed by patterns and locations used for etching a gate insulating layer and a gate electrode. Therefore, types of device designs are limited.